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ASIC Physical Design LeadAbout NiobiumAt Niobium Microsystems, we develop high performance microelectronic products to enable the secure collection, processing, and distribution of critical data. We are a trusted partner of government research teams and commercial customers whose solutions require lower power, higher efficiency, and proven security.Founded as a 2021 spinout from Galois, Inc., a world-class security and computing systems research and development company, our team combines decades of experience in advanced semiconductor design with a record of delivering world class solutions.About This RoleWe are seeking a highly experienced ASIC Physical Design Lead to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 10+ years of hands-on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally.In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power-efficient silicon across cutting edge technology nodes.ResponsibilitiesAs the Physical Design Lead, you will be responsible for:End-to-End Physical Implementation LeadershipOwn and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery.Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow.Floorplanning & SoC IntegrationArchitect and execute floorplanning strategies for large, hierarchical SoCs, including:IP integration and macro placementPhysical partitioning and hierarchy definitionPower grid architecture and clock distribution topologyDIE size, aspect ratio, and physical constraintsCollaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets.Place & Route + Timing ClosureLead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys).Drive timing convergence across corners, modes, voltage domains, and operating conditions.Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity.Clocking, Power, and Sign-OffImplement CTS and drive skew, latency, and clock power optimization.Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC).Integrate and validate low power methodologies, including UPF/CPF flows.Cross-Functional Collaboration & Quality OwnershipPartner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean.Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing.Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout.Leadership & MentorshipProvide technical leadership to a team of junior and mid-level physical designers.Mentor, coach, and guide engineers in methodology, debug, and best practices.Champion continuous improvement across flows, scripts, and design methodology.Key QualificationsEducationBS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field. (Advanced degree preferred for leadership roles.)Required Technical Expertise10+ years of relevant experience in ASIC Physical Design, with a strong track record of multiple tape-outs at advanced technology nodes (16nm → 3nm preferred).Deep expertise in:FloorplanningPlace & RouteCTSSTA/Timing ClosurePhysical verification & sign-offPower integrity (IR drop/EM)Low power design and UPFStrong hands on proficiency with Cadence and/or Synopsys physical design toolchains.Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities.Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans.Required General SkillsStrong communication skills—able to articulate technical decisions across cross-functional teams.Highly motivated, proactive, and able to operate effectively in a distributed team environment.Comfortable owning schedules, deliverables, and quality in a fast-moving development cycle.Exceptional analytical, debugging, and problem-solving skills with a meticulous attention to detail.LocationNiobium is headquartered in Columbus, Ohio with additional locations in Fayetteville, Arkansas, Portland, Oregon, and Dayton, Ohio. We will not be limited by geography for the right candidate.BenefitsNiobium offers a highly competitive benefits program to support employees and their families, including:Competitive salaries Equity in the form of Incentive Stock Options (ISO)Employer paid medical insurance planHealth Savings Account (HSA) with employer contributionsDental and vision reimbursement account (HRA)401(k) retirement plan with employer matchFlexible work location with remote optionsFlexible time off

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